When fabricating an integrated circuit, and as is well known, a series of layers are deposited on a substrate (usually a crystalline silicon substrate) and are patterned and etched to form a circuit. For the circuit to work properly, it is important that each subsequent layer be aligned with the previously formed layer or layers, at least within some permissible tolerance.
To align the various layers, and referring to FIG. 1A, a substrate 12 having a photoresist applied thereon (not shown) is placed in a photolithographic chamber 10, sometimes referred to as a “stepper” or “scanner.” In the stepper 10, a mask or reticle 27 is used to pattern the photoresist. As the patterned photoresist ultimately dictates the positioning of the underlying circuit layer to be etched, its alignment is critical.
To bring the substrate 12 into alignment with the mask 27, an image of some structure on the mask and some structure 24 on the wafer are compared using well-known optical analysis equipment 14, with such images being received by optical sensors 20. If alignment is needed, the optical analysis equipment 14 can control the positioning of a chuck 16 on which the substrate 12 sits via motor stages 18, which, for example, can move the chuck 16 along the X-axis, Y-axis, or rotational θ-axis as appropriate. Such alignment is usually assessed at numerous locations around the substrate 12's perimeter, which accordingly requires reference to a plurality of alignment structures 24 on the substrate 12, as shown in FIG. 1B. However, reference to a single alignment marker could also be used.
Although alignment structures 24 can constitute an actual active portion of the circuit being fabricated, a dedicated inactive structure is usually formed for this purpose—what is referred to as an alignment marker. Referring to FIG. 1B, such alignment markers 24 are typically formed outside of the active integrated circuit area 22 on the wafer, i.e., in the area in which the substrate will be scribed or “diced” for later insertion into packages. A simple “cross” pattern is illustrated for the alignment marker 24, but as one skilled in the art will understand, such markers can come in a variety of different shapes and sizes (e.g., chevrons, gratings, squares, etc.), depending on the alignment task be performed. Typically, more than one alignment marker 24 is fabricated on the substrate 12 as shown, which may range from approximately 20 to 500 microns in size.
However, alignment markers appearing on the side of the substrate from the problem that such markers may eventually become coverd with opaque materials during later processing steps, and hence may become difficult for the opitcal sensors 20 to “see,” as discussed at length in above-incorporated U.S. patent application Ser. No. 10/840,324.
Accordingly, the prior art has experimented with the use of back side alignment markers. As their name suggests, back side alignment markers are located on the opposite side of the substrate from the front side where the active circuitry is formed. The processing steps used to form the active circuitry on the front side generally do not appreciably affect the back side; for example, materials deposited on the front side of the substrate will generally not find their way to the back side, except in trace amounts. Accordingly, back side alignment markers generally remain unaffected during processing of the substrate, and therefore remain visible to the optical sensors 20 for alignment purposes.
An exemplary stepper chamber 30 relying on the use of back side alignment markers 27 is shown in FIG. 2. Such a chamber is generally similar to the chamber 10 of FIG. 1, but includes holes 17 in the bottom of the chuck 16 aligned with the backside alignment markers 27. Mirrors 15 direct light between the back side alignment markers 27 and the optical sensors 20 to allow the alignment markers 27 to be “seen” for alignment purposes. Alternatively, channels through the chuck and parallel to the substrate 12's surface can carry the optical path between the back side alignment markers 27 and the optical sensors 20, such as is disclosed in http://www.minanet.com/documents/ASML.pdf (Sep. 25, 2003), which is submitted herewith and which is incorporated by reference in its entirety.
However, back side alignment markers still suffer from processing difficulties, as illustrated by the process of FIG. 3, which shows how such back side alignment markers are traditionally formed. FIG. 3A shows in cross section a blank or stating substrate 12, which again is usually a silicon crystalline substrate. The substrate 12 has a front side 12a and a bottom side 12b. Prior to fabrication of the integrated circuit on the front side 12a, the front side is highly polished, rendering the front side 12a to near perfect smoothness at the atomic level that is appropriate for the formation of transistors and the like. The back side 12b is generally also smooth, but usually not as smooth as the front side 12a. 
Traditionally, the back side alignment markers 27 are formed using traditional photolithography techniques. However, care must be taken to protect the near-perfectly smooth front side 12a, as this surface is easily scratched. If scratched, the electrical structures (such as transistors) eventually formed at the front side 12a will “leak” current and otherwise may perform poorly from an electrical standpoint. Accordingly, before formation of the back side alignment markers 27, a protective layer 40 is formed on the front side 12a, as shown in FIG. 3B. Typically, this protective layer 40 constitutes a silicon dioxide or silicon nitride layer.
With the front side 12a protected, photolithography processing on the back side 12b can now begin. Accordingly, and referring to FIG. 3C, the substrate 12 is inverted and placed front side 12a down onto a work surface 42, which varies throughout the back side alignment marker formation process but which initially would comprise a photoresist spinning apparatus. A photoresist 41 is deposited (spun) on the back side 12b, and is moved to a stepper apparatus, where it is exposed using a mask having the desired back side alignment marker 27 pattern (not shown) and developed to expose the back side 12b through the photoresist (FIG. 3D). The substrate 12 is then moved to an etching chamber (not shown) where the alignment marker is etched into the back side 12b using the remaining photoresist as a masking layer (FIG. 3E). Thereafter, the remaining photoresist 41 is stripped (not shown), and the protective layer 40 is etched away (not shown), thus leaving the back side alignment marker 27 on the back side 12b of the substrate 12 (FIGS. 3F and 3G). Thereafter, the substrate 12 can be processed to form an integrated circuit, using the back side alignment marker 27 (or markers) to align the substrate 12 with each mask during sensitive photolithography steps in chamber 30 (FIG. 2).
However, it should be appreciated from the foregoing that formation of the back side alignment markers 27 involves a lot of preparation—protective layer formation, photoresist deposition, patterning and removal, etching, removal of these layers, etc.—before processing of the substrate 12 can begin in earnest to form active useful structures on the front side 12a. Accordingly, the art would be benefited by improved methods for forming back side alignment markers, and in particular methods that forego these additional steps. This disclosure provides solutions.